1. Field of the Invention
This application relates generally to an improved high power, impulse magnetron sputtering method and system, and more specifically to a high power, impulse magnetron sputtering method and system including synchronized delivery of a high-frequency signal to generate a maximum self bias voltage that occurs substantially simultaneously with a maximum DC current during a DC voltage pulse.
2. Description of Related Art
Semiconductor chips face constant development aimed at increasing the performance of circuits supported by the chips while decreasing the overall physical size of the chips. Physical limitations like power dissipation in integrated circuits (“ICs”) and the process technology for fabricating ICs on an ever smaller scale have recently encouraged vertically stacking a plurality of chips instead of further increase the lateral device density to enhance performance. For example, current wire bonding techniques are limited in how closely spaced in a lateral dimension circuit elements can be formed on a semiconductor chip and electrically connected together using that technique. To allow further expansion of such devices the semiconductor chip can be enlarged to accommodate the additional circuit elements, but this leads to an enlargement of the overall size of the semiconductor chip rather than a reduction in size.
Instead of making the semiconductor chip larger in the lateral dimension, two or more substantially planar semiconductor chips or layers can be stacked vertically (i.e., their planar faces mated together) to provide the required area on the semiconductor chip to support the additional circuit elements. This so-called 3D integration of vertically stacked semiconductor chips can be utilized in a variety of different applications approaching maximum device density, such as computer memory, electro-optical devices, microelectromechanical (“MEMS”) devices, sensors, above IC imagers, displays, as well as other technologies.
The vertically-stacked semiconductor chips are fabricated to include through-silicon vias (“TSVs”) to establish electrical connections between the vertically-stacked semiconductor chips, and may include other high aspect ratio structures. The TSVs are high aspect ratio holes in the semiconductor chips that are plated with a metal or other suitable conductor to electrically connect two or more layers of circuit elements. Traditionally the TSVs have been formed by laser drilling or dry etching cavities into a top surface of the semiconductor chip's substrate, and an interior periphery of said cavities are then plated with a metal or other suitable conductor. A bottom surface of the substrate is then ground until the metal within the cavities is exposed at the bottom surface of the semiconductor chip to be stacked.
In order to minimize the surface area of each TSV exposed at the bottom surface of the semiconductor chip and utilize a substrate thickness that is manageable for the desired application, each TSV typically has an aspect ratio of at least 10:1, and possibly 20:1 or more in the future. Such high aspect ratios make it difficult to effectively plate the interior periphery of the cavities formed in the substrate with consistency using conventional deposition techniques.
Accordingly, there is a need in the art for a method and apparatus for forming a TSV in a substrate of a semiconductor chip for electrically connecting a plurality of semiconductor chips.